A General Introduction To Cache Coherence
Summary: The concept of cache coherence may be relatively new to you, but it’s a relatively important computer field concept. So today, this page will give you a general introduction to cache coherence.
In computer architecture, cache coherence is the consistency of shared resource data, which is eventually stored in multiple local caches. Problems can occur with incoherent data when clients maintain caches of common memory resources, especially common for CPUs in multiprocessing systems.
Each processor has a separate cache memory in a shared-memory multiprocessor system. It’s likely to have many copies of the shared data: one copy in the primary memory and one in the local cache of each processor requesting it.
If one of the copies of the data changes, the other copies must reflect the change. Cache coherence is a discipline, and it ensures that changes in shared operands (data) values propagate throughout the system promptly.
The following part lists the requirements for cache coherence.
- Write Propagation: Data changes in any cache must be propagated to other copies in the equivalent cache.
- Transaction Serialization: All processors must view Reads/Writes to a single memory location in the same order.
Theoretically, coherence can be implemented at load/storage granularity. However, in practice, it is usually executed at the cache block granularity.
Coherence defines the behaviour of reading and writing to a single address location. A type of data that appears simultaneously in the different cache memory is called cache coherence. It is also called global memory in some systems.
In a multiprocessor system, more than one processor has cached a copy of the memory location X. To achieve cache coherence, it is necessary to meet the following conditions.
- When the processor P reads the location X after the write by the same processor Pto X and the write to X by another processor does not appear between the write and the read instruction by P, X must always return a value written by P.
- When processor P1 reads location X, another processor writes from P2 to X, and any other processor writes to X occur between two accesses, and the reads and writes are sufficiently separated. X must always return a value written by P2.This condition defines the concept of a coherent view of memory. Propagation of writes to shared memory locations makes sure that all caches have a coherent view of memory. If the processor P1 reads X’s old value, we can say that memory is incoherent even after P2 is written.
The above conditions meet the Write Propagation conditions required for cache coherence. But they are not adequate because they do not meet Transaction Serialization criteria.
There are two most common mechanisms for ensuring coherency: snooping and directory-based, each with its advantages and disadvantages. If enough bandwidth is available, Snooping-based protocols tend to be faster because all transactions are requests/responses that all processors see.
The disadvantage is that snooping has no scalability. Each request must be broadcast to all nodes in the system, which means that as the system grows large, the bus’s size and the bandwidth it provides must increase.
On the other hand, directories tend to have longer latency, with three hop requests/forwards/responses. However, directories use much less bandwidth because messages are point-to-point rather than broadcast. As a result, many large systems adopt this kind of cache coherence.
The consistency protocol applies cache consistency in multiprocessor systems. The goal is to ensure that two clients must not see different values in the same shared data.
The protocol must achieve the basic demands of coherence, tailored to target systems or applications.
Protocols can also be categorized as snoopy or directory-based. Typically, early systems adopted directory-based protocols, where directory tracks shared data and sharers. Transaction requests are sent to all processors in a snoopy protocol. All processors monitor requests and respond appropriately.
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